基于CPLD器件的FIR滤波器的设计

基于CPLD器件的FIR滤波器的设计 The Design of FIR Filter Based on CPID Devices 韩德红 HAN De-hong~1 1 2 3 first-author 石新智 SHI Xin-zhi~2 1 2 3 空军雷达学院基础部 空军雷达学院基础部 Department of Basic Courses, Air Force Radar Academy Department of Basic Courses, Air Force Radar Academy 武汉大学计算机学院,湖北,武汉,430010 武汉大学计算机学院,湖北,武汉,430010 School of Computer,Wuhan University School of Computer,Wuhan University ,湖北,武汉,430072 ,湖北,武汉,430072 给出了一种适合于用CPLD器件实现有限冲击响应（FIR）滤波器的补码算法.用Lattice公司的is pLSI8840器件设计了8阶、11位的线性相位FIR滤波器,并提出了用多片CPLD器件进行扩展设计的方法,实现了更高阶的线性相位FIR滤波器.通过小型乘法查找表和具有超前进位的流水线加法器实现FIR滤波器的设计,提高了工作速度,节约了器件资源,其最高工作频率可达60MHz.在计算机上进行了硬件仿真分析,并将仿真结果与理论计算结果进行了比较.表明该滤波器工作可靠,精度高,具有较好的实用价值. the Complement Arithmetic of FIR filter fit with CPLD Devices was given. The 8-tap,11-bit FIR filter with 16-bit output was designed with one lattice ispLSI8840,and the design mathod of more taps FIR filter built with multiple CPLDS are proposed. In order to improve the operating frequency FIR filter and econmize the hardware resources, the design of FIR filter are realized by using lesser look-up-tables（LUT） and carry look-ahead adders with pipelined operation. operating frequency of the filter is up to 60 MHz. Made the simulation by means of computer,and compared the result of simulation with theoretical calculation.The results demonstrate that the filter is reliable and high-precision. 数字信号处理 FIR滤波器 复杂PLD 在系统可编程逻辑器件 DSP（digital signal processing） FIR Filter CPLD（complex programmable logic device） in-system programmable logic device TN713 国家"十五"计划资助项目（2001AA632050） 2004-01-01 2021-04-01 1