应用于安全处理器的RSA/SHA复用加密单元设计

应用于安全处理器的RSA/SHA复用加密单元设计 Unified Crypto Architecture Accelerating RSA/SHA for Security Processor 韩林 HAN Lin 1 first-author 韩军 HAN Jun 1 曾晓洋 ZENG Xiaoyang 1 黄伟 HUANG Wei 1 复旦大学专用集成电路与系统国家重点实验室 复旦大学专用集成电路与系统国家重点实验室 State Key Laboratory of Application Specific Integrated Circuit and System,Fudan University State Key Laboratory of Application Specific Integrated Circuit and System,Fudan University 提出了一种加速RSA和SHA算法的复用硬件架构设计方法,通过在RISC处理器中集成一种RSA/SHA复用加密单元来取得高效的密码运算能力.以一种使用该加密单元的安全处理器来验证该方案的有效性,结果表明密钥长度为1 024位的RSA算法执行时间为190 ms,SHA-1的吞吐率达到64 Mb/s.本方案采用SMIC0.18μm标准CMOS工艺进行了逻辑综合,RSA/SHA复用加密单元的最高时钟频率可达到196 MHz,核心电路面积约为2600个等效与非门. This paper proposes a unified hardware architecture which can accelerate both RSA and SHA-1 calculations.And a scalable and unified crypto function unit is presented to support high performance cryptographic computation in the RISC-like processor.To evaluate the effectiveness of our solution,a crypto-processor is employed to integrate the proposed function unit,and the execution time of 1 024 bit RSA is 190 ms and SHA-1 encryption rate reaches 64 Mbps.According to the synthesis results based on SMIC 0.18 micron library,the unified crypto function unit can achieve 196 MHz work frequency with the utilization of 2.6 thousand gates. RSA算法 安全散列算法 RSA/SHA复用加密单元 RISC处理器 RSA（Rivest-Shamir-Adleman） algorithm SHA（secure Hash algorithm） algorithm unified RSA/SHA crypto function unit RISC（reduced instruction set computer） processor TP309.7 国家自然科学基金资助项目（60576024,60776028） 2008-05-01 2021-04-01 5